This application claims priority to an application entitled xe2x80x9cParity Checking Device and Method in Data Communication Systemxe2x80x9d filed in the Korean Industrial Property Office on Dec. 29, 1999 and assigned Serial No. 99-65241, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates generally to an error checking device and method in a data communication system, and in particular, to an error checking device and method using parity checking.
2. Description of the Related Art
A data communication system exchanges data between a transmitter and a receiver. Errors may occur in the exchanged data according to the communication environment between the transmitter and the receiver. Hence, the data communication system needs to check for possible generated errors in the received data and correct them. A popular error checking method is parity checking.
According to a conventional error checking method utilizing parity checking, after data is shifted on a bit basis, it is determined whether a carry (e.g., value xe2x80x9c1xe2x80x9d) has been generated after the bit shift, and the number of carries are counted. If all the bits of the data are completely shifted, the resulting count value is subjected to modulo-2 addition and it is checked whether the remainder of the modulo-2 addition is xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d to thereby determine whether the data has errors. Consequently, the conventional parity check method is the process of determining whether data has errors depending on whether the data has an odd or even number of 1s.
FIG. 1 is a flowchart illustrating the conventional parity check method in a data communication system.
Referring to FIG. 1, a loop count and a carry count are set to 0s in step 110 and data is shifted by one bit in step 120. It is determined whether a carry has been generated after the shift in step 130. Upon generation of a carry, the carry count is increased by 1 in step 140. If the carry is not generated in step 130 or the carry count is increased in step 140, the loop count is increased by 1 in step 150. In step 160, it is determined whether all the bits of the data have been shifted completely by comparing the loop count with the length of the data. If the loop count is greater than or equal to the data length, it is determined that all the bits of the data have been shifted completely.
If it is determined that all the bits of the data are not shifted in step 160, steps 120 to 160 are repeated. On the other hand, upon completion of the bit shifts in step 160, the carry count is modulo-2 added in step 170. It is determined whether the data has an error based on the remainder of the modulo-2 addition in step 180. Since the carry count is divided by 2, the remainder is 0 or 1. For example, if the remainder is 1, it may be considered that an error has occurred and if it is 0, it may be considered that the data has no errors.
In the foregoing conventional parity check method, a decision is made as to whether a carry has been generated in a loop at every bit shift of the data. Thus, time required for error check increases in proportion to the number of the bits of the data. For example, if the data has 2n bits, the loop must occur 2n times.
It is, therefore, an object of the present invention to provide a parity checking device and method in which a parity check is performed on data for a reduced time in a data communication system.
It is another object of the present invention to provide a parity checking device and method in which a parity check is performed on 2n-bit data by repeating a loop (nxe2x88x921) times (i.e., n loop occurrences) in a data communication system.
It is a further object of the present invention to provide a parity checking device and method utilizing XOR operations in a data communication system.
It is still another object of the present invention to provide a parity checking device and method in which a parity check is performed on data through iterative XOR operations between the upper half bit sequence and lower half bit sequence of the data, and the presence or absence of errors is determined based on the final XOR operation result.
To achieve the above and other objects, there is provided a parity checking device and method in a data communication system. In the parity checking device, a controller determines loop occurring times according to the length of the data and the number of bits to be shifted according to the data or XOR operation results and determines whether the data has an error based on a final XOR operation result. A first register and a second register store the data or the XOR operation results under the control of the controller. A shifter receives the output of the first register and shifts the received bits by the shift bit number received from the controller. An operation unit receives the outputs of the shifter and the second register, performs an XOR operation between the received data from the shifter and second register, and outputs an XOR operation result under the control of the controller.
It is determined whether the data has an error based on a final XOR operation result after as many XOR operations as the loop occurring times are performed.